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As a registered user you have some advantages like theme manager, comments configuration and post comments with your name.    Verification Guild: Forums  Forum FAQ   Search   Usergroups   Profile  Digest    Log in  Simulation Moderator: Janick Bergeron Users browsing this forum: None Goto page 1, 2  Next    Verification Guild Forum Index -> Simulation Mark all topics read  Topics   Replies   Author   Views   Last Post  VHDL: Connecting IO's together within the same module 3 dmcnam 11842 Thu Dec 16, 2004 4:19 am dmcnam VHDL help required 8 phil583 7762 Wed Nov 17, 2004 7:16 am hemanth cycle accurate model of RISC CPU 2 stevenyytan 4622 Wed Nov 17, 2004 4:34 am FaultFinder Techniques: Know-how in creating effective and speedy TBs 12 SAHO 12068 Wed Nov 10, 2004 2:59 pm SAHO How to randomize the seed for $random from one test to next? 9 bricks 9180 Mon Nov 08, 2004 12:24 pm srini Question : Know - How on implementing smart testbench 12 SAHO 9552 Fri Nov 05, 2004 10:57 pm srini Question : HDL simulation evolution 2 SAHO 3694 Sat Oct 30, 2004 5:15 pm Logger What simulator do you use? 8 cschalick 7701 Fri Oct 29, 2004 6:49 am vhdlcohen Virtual CPU Co Verification tool 3 Anoop 4917 Thu Oct 28, 2004 2:20 pm jra stimulus vector generation 3 thebamaman 4858 Wed Oct 27, 2004 10:03 am asif Co - Verification 8 Anoop 7383 Tue Oct 26, 2004 4:40 am Anoop How can I get Vera Classes to interract. 2 vishaln 4579 Mon Oct 25, 2004 11:21 pm vishaln Why replace VHDL testbenches with SystemC testbenches ? 2 SAHO 5003 Mon Oct 25, 2004 8:43 pm alexg Random stability in Vera. 3 mbowler 4597 Thu Oct 21, 2004 8:04 am mbowler Save/Restart with NC/Specman and Denali 1 EdA 5668 Wed Oct 20, 2004 8:10 am EdA Instantiation in vera 2 muthu 4302 Fri Oct 15, 2004 12:07 am muthu Vera port/binding question: 3 jmcneal 4818 Thu Oct 14, 2004 11:18 am Janick Resetting TB state 3 Bren 4217 Tue Sep 21, 2004 6:38 am Ajeetha Open source SystemVerilog? 8 Martin1234 7613 Tue Aug 31, 2004 3:53 am Darren Why Do I need to use a task? 2 bebic 4312 Wed Aug 25, 2004 4:54 am laurentclaudel Clock skew in RTL simulation 6 PaulUiterlinden 9480 Sat Aug 14, 2004 8:08 pm Janick Books on Vera 1 unmesh 4204 Mon Aug 09, 2004 5:05 pm Larry connecting VERA class variables to HDL ports 2 unmesh 4100 Thu Aug 05, 2004 11:05 pm unmesh Reusing C tests and Verilog tests in Vera 1 VeraNewbie 4138 Thu Jul 29, 2004 1:48 am verif_eng What is the Best Cost Effective Verification Approach Here? 1 postgenerate 4745 Mon Jul 19, 2004 8:05 am wsnyder Reasons for System Verilog logic and reg types 3 quioxl 6698 Sun Jul 18, 2004 3:34 pm knoecksj Writing testbenches when using an emulator 9 romi 9294 Sun Jul 18, 2004 9:20 am postgenerate SystemC for func ver of Verilog-RTL in ModelSim? 1 Watchman 3798 Sat Jul 17, 2004 9:57 pm postgenerate Future Verification Language ??? 4 snoyfrancis 6457 Wed Jul 07, 2004 9:44 pm vhdlcohen System Verilog vs VERA 4 valipep 10187 Tue Jul 06, 2004 7:10 am alexg Dereferencing signals in a VHDL testbench 6 powersurge 7922 Tue Jun 29, 2004 3:03 pm JimLewis Modeling large memories in Verilog 2 urmiaboy 4551 Wed Jun 16, 2004 3:41 pm Logger SV constraint solver/randomisation 2 elavelle 4269 Wed Jun 16, 2004 9:55 am elavelle VPI FAQ? 0 EdA 3128 Fri May 14, 2004 10:20 am EdA Conditional compilation 5 aliss 6503 Sat May 08, 2004 12:53 pm srini How to monitor verilog events in specman E? 1 lichen_xin 4135 Fri Apr 30, 2004 1:15 pm Leo Debugging long random simulations [ Goto page: 1, 2 ] 16 Newsletter 12198 Sat Apr 24, 2004 6:07 am z Writing dynamic random tests generator 1 crystal 4157 Fri Apr 09, 2004 9:32 am cabriggs Random Generation in Verilog 3 spauls 16473 Thu Apr 08, 2004 1:52 pm alexg VCS-mx Problems with Specman? 1 Mike 3810 Thu Apr 01, 2004 12:39 pm Mansour Runing batch simulations across many unix machines. 0 richardbradley 3084 Tue Feb 10, 2004 1:38 pm richardbradley Any good suggestion for a Specman textbook? 1 hevangel 4277 Mon Feb 02, 2004 12:23 pm Sean_W_Smith Why Be Concerned With Simulation Performance? 11 postgenerate 7811 Wed Jan 28, 2004 12:58 pm alain How to avoid duplicate modules in Verilog 2 Newsletter 3403 Mon Jan 12, 2004 1:15 pm mcurry Want to know more about Verilog race conditions 1 Newsletter 3321 Sun Jan 11, 2004 4:26 pm RobertClark Reference vs behavioral model 3 Newsletter 3798 Mon Jan 05, 2004 10:37 pm Newsletter To gate-level sim or not gate-level sim? 0 Newsletter 2991 Mon Jan 05, 2004 10:33 pm Newsletter Where to download the source code for Jeda? 0 Newsletter 2826 Wed Dec 17, 2003 5:49 pm Newsletter Seeking opinion on Jeda 2 Newsletter 2512 Mon Dec 01, 2003 12:00 am Newsletter Seeking opinion about a testbench generator tool I wrote 0 Newsletter 1403 Mon Dec 01, 2003 12:00 am Newsletter Display topics from previous: All Topics1 Day7 Days2 Weeks1 Month3 Months6 Months1 Year     Verification Guild Forum Index -> Simulation All times are GMT - 5 Hours Goto page 1, 2  Next Page 1 of 2 Jump to: Select a forum Main----------------MainEDA NewsCommunity Services Networking----------------Looking for a jobLooking for candidates Archives----------------AssertionsCoverageFormalSimulationDesignMiscellaneous Test----------------Test  New posts    No new posts    Announcement New posts [ Popular ]    No new posts [ Popular ]    Sticky New posts [ Locked ]    No new posts [ Locked ] You can post new topics in this forum You can reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum Forums ©

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