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paolo
Senior
Joined: Apr 15, 2008
Posts: 22
Location: Santa Cruz
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 Posted: Mon Nov 23, 2009 4:29 pm Post subject: parameter struct type issues in VCS |
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Hi
I'm encountering some differences in how Mentor and Synopsys simulators determine whether parameter values are compile time constants. I'm hoping someone here can shed some light on this.
In my scenario I have modules with long lists of parameters (20+) and various modules in my design share the same list of parameters. Since SystemVerilog allows parameters to have types other than integer, I figured I'd pack these parameters all into a struct type in order to make the code more concise. The idea is to do for parameters what Interfaces do for lists of ports.
The code is below and it works great in the Mentor simulators. VCS however complains at compile time that the parameters are not constant.
Any ideas?
Thanks,
Paolo
| Code: |
package types_pkg;
typedef struct packed {
int WIDTH;
int DEPTH;
} my_param_t;
parameter my_param_t my_param_default =
{
32'd16 , // WIDTH
32'd8 // DEPTH
};
endpackage
interface my_if(
clk,
reset
);
import types_pkg::*;
input clk;
input reset;
parameter my_param_t PARAM = my_param_default;
logic [PARAM.WIDTH-1:0] a;
logic [PARAM.WIDTH-1:0] b;
modport foo (
input a,
output b
);
endinterface
module my_module (
input clk,
input reset,
my_if.foo my_ports
);
import types_pkg::*;
parameter my_param_t PARAM = my_param_default;
logic [PARAM.WIDTH-1:0] aa;
logic [PARAM.WIDTH-1:0] [0:PARAM.DEPTH-1] bb;
int i;
always @(posedge clk) begin
if (reset) begin
bb <= '0;
end else begin
bb[0] <= my_ports.a;
for (i=1; i<PARAM.DEPTH-1; i=i+1) begin
bb[i] <= bb[i-1];
end
end
end
assign my_ports.b = bb[PARAM.DEPTH-1];
endmodule
module top ();
import types_pkg::*;
parameter my_param_t the_param = {
32'd32,
32'd8
};
bit clk, reset;
initial begin
reset <= 1'b0;
clk <= 1'b0;
forever #5 clk <= ~clk;
end
my_if #(
.PARAM(the_param)
)
the_bus (clk,reset);
my_module #(
.PARAM(the_param)
)
the_module (clk,
reset,
the_bus.foo);
endmodule
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5S63
Senior
Joined: Jan 07, 2004
Posts: 23
Location: Ottawa, Ontario, Canada
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| Posted: Mon Nov 30, 2009 10:00 am Post subject: |
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| Looks like a bug in VCS! |
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paolo
Senior
Joined: Apr 15, 2008
Posts: 22
Location: Santa Cruz
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| Posted: Fri Jan 08, 2010 7:02 pm Post subject: VCS bug? |
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| 5S63 wrote: | | Looks like a bug in VCS! |
That's what I suspect also. Is anyone from Synopsys reading this? |
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cabriggs
Senior
Joined: Jan 12, 2004
Posts: 90
Location: Massachusetts
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glb
Senior
Joined: Feb 02, 2005
Posts: 114
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| Posted: Mon Jan 11, 2010 11:55 am Post subject: |
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Not sure about the bug, but I like the trick.
Done similar with VHDL - it's a neat way to bundle the params/generics.
I think we ended up writing a function for the 'my_param_default' part though, since it lets you only care about setting some parameters and keep the rest at default. Otherwise I think you'd have to specify the whole literal struct value. That gets cumbersome too. |
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glb
Senior
Joined: Feb 02, 2005
Posts: 114
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| Posted: Mon Jan 11, 2010 1:03 pm Post subject: |
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Not sure about the bug, but I like the trick.
Done similar with VHDL - it's a neat way to bundle the params/generics.
I think we ended up writing a function for the 'my_param_default' part though, since it lets you only care about setting some parameters and keep the rest at default. Otherwise I think you'd have to specify the whole literal struct value. That gets cumbersome too. |
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just_be_frank
Newbie
Joined: Oct 12, 2007
Posts: 1
Location: Kalifornia
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| Posted: Fri Jan 22, 2010 4:31 pm Post subject: |
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Paolo,
This should be legal and needs to be fixed. I have opened a case for you, please do contact support: vcs_support@synopsys.com or get in touch with your Application Engineer so we can file this properly and prioritize the request accordingly. (case 8000368333)
Regards,
Frank
P.s. If my guess is right you know me and can contact me too  |
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paolo
Senior
Joined: Apr 15, 2008
Posts: 22
Location: Santa Cruz
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| Posted: Fri Feb 26, 2010 3:21 pm Post subject: |
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Thanks for the follow up Frank!
I'll try it when the next release of VCS comes out.
As an aside, one of the things I feel is missing in the SystemVerilog language spec is a mechanism to bundle parameters and pass them around. This hack addresses that issue, but it would be nice to support something like this formally. We have interfaces for bundling groups of ports. Now, how about something like parameter objects? Just a thought.
Paolo.
PS - Your guess is correct |
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dave_59
Senior
Joined: Jun 22, 2004
Posts: 710
Location: San Jose
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| Posted: Mon Mar 01, 2010 12:38 am Post subject: |
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Paolo,
Not quite sure what you think is missing from SV. Why is a struct not a good enough bundle? You can also you a class with a list of parameters, and that class can be extended to override and add additional parameters.
Dave Rich |
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tessitd
Senior
Joined: Sep 05, 2006
Posts: 286
Location: Colorado
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| Posted: Mon Mar 01, 2010 11:38 am Post subject: |
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Dave,
When I first read this solution I thought it was slick -- but then went back to how I handled it in my current designs and indeed I just used a class to carry around the parameters; with all of your aforementioned power. What I haven't tried is using a class with Synthesizable SystemVerilog? Is this a solution to that issue and happens to work with the SVTB part of the language?
TomT... |
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paolo
Senior
Joined: Apr 15, 2008
Posts: 22
Location: Santa Cruz
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| Posted: Wed Mar 10, 2010 4:06 pm Post subject: |
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Dave,
Sure, using the struct to bundle parameters and pass them around is good starting point, but I'd also like to include some validation code. Validation code would check that a set of initialized parameter values are consistent with the constraints of the application. So, for something like that, I would need a class. As I mentioned previously, interfaces bundle ports and also permit the addition of code. Interfaces are supported both in simulation and synthesis tools, but classes are not supported in synthesis tools, as far as I know. Tom has pointed out the dilemma in the previous post.
Paolo |
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dave_59
Senior
Joined: Jun 22, 2004
Posts: 710
Location: San Jose
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| Posted: Wed Mar 10, 2010 5:18 pm Post subject: |
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There's nothing inherently un-synthesizable about a class, given a set coding guidelines, just as there are in what is commonly accepted as synthesizable RTL code. It's just that no one has found the investment in the effort worth their time.
Verification code is not synthesizable because no one wants it to be (except the emulation folks  ).
So whether you wrap a struct in a class or interface for verification doesn't really matter. In either case you have the struct to pass to your RTL.
Dave |
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